1. Technical Field
The present invention relates in general to testing and verification, and in particular to verification of digital designs. Still more particularly, the present invention relates to a system, method and computer program product for verification of digital designs unidirectional bus verification.
2. Description of the Related Art
With the increasing penetration of processor-based systems into every facet of human activity, demands have increased on the processor and application-specific integrated circuit (ASIC) development and production community to produce systems that are free from design flaws. Circuit products, including microprocessors, digital signal and other special-purpose processors, and ASICs, have become involved in the performance of a vast array of critical functions, and the involvement of microprocessors in the important tasks of daily life has heightened the expectation of error-free and flaw-free design. Whether the impact of errors in design would be measured in human lives or in mere dollars and cents, consumers of circuit products have lost tolerance for results polluted by design errors. Consumers will not tolerate, by way of example, miscalculations on the floor of the stock exchange, in the medical devices that support human life, or in the computers that control their automobiles. All of these activities represent areas where the need for reliable circuit results has risen to a mission-critical concern.
In response to the increasing need for reliable, error-free designs, the processor and ASIC design and development community has developed rigorous, if incredibly expensive, methods for testing and verification for demonstrating the correctness of a design. The task of hardware verification has become one of the most important and time-consuming aspects of the design process. In order to maximize the verification coverage attainable with the resources available to a hardware design team, numerous verification methods have been developed, each with their own strengths and weaknesses.
Among available methods, the use of on-chip trace and debug buses has become popular. On-chip trace and debug buses are used to monitor internal nodes that cannot be readily routed to chip pads due to package limitations. These buses represent a unidirectional tree structure and can be configured to route individual inputs to external pads or internal debug entities (like trace logic analyzer or performance monitor logic) by configuring multiplexors and on-bus ramps appropriately. These buses also contain non-configurable elements such as interfaces between different clock domains (e.g., speed converters).
Due to the high complexity of recent chips, these buses have reached a significant complexity in terms of the number of primary inputs and the number of configuration modes. Verification of these buses is difficult because only a very limited number of bus configuration scenarios can be simulated and checked for correct connectivity in a reasonable amount of time with the methods available in the prior art. Any errors in such bus logic that slip into silicon are not only expensive to rectify; they also greatly jeopardize the ability to utilize the fabricated design for any purpose in the bring-up lab, to a degree even greater than for other functional errors.
What is needed is an automated method and system for formal verification of unidirectional on-chip trace and debug buses to reduce manual effort in verification process.